Abstracted nand logic in stacks

Final Office ActionLatest

Aug 7, 2025 · §103

Final Office Action — all claims 1-23 and 51-53 rejected under §103 obviousness over Ramachandra and combinations

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Rejection groups (5)

§ 103Obviousnessclaims 1-3, 5-13, 18-23, 53

Claims 1-3, 5-13, 18-23 and 53 are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandra et al. (U.S.

Examiner theory

Publication No. 2018/0102344) (“Ramachandra”) in view of Hirano et al. (U.S. Publication No. 2019/0341375) (“Hirano”) and Tao et al. (U.S. Publication No. 2018/0040587) (“Tao”). [1] With respect to the limitations of claim 1, Ramachandra teaches a microelectronic package, comprising: a substrate (Ramachandra; see #20 in Figure 2 and in ¶ [0018]) having first and second opposite surfaces (bottom and top surfaces) each extending in first and second orthogonal directions (into the page and left to right); a NAND wafer (id.; see #24 in Figure 2 and in ¶ [0020], “NAND” in [0029]) having a memory storage array (id.; see #126 in Figure 2 and in ¶ [0029]) therein, the NAND wafer having element contacts (id.; see #66 in Figure 3 and in ¶ [0025]) electrically connected with electrically conductive s

§ 103Obviousnessclaims 4

Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ramachandra et al. (U.S.

Examiner theory

Publication No. 2018/0102344) (“Ramachandra”) in view of Hirano et al. (U.S. Publication No. 2019/0341375) (“Hirano”) and Tao et al. (U.S. Publication No. 2018/0040587) (“Tao”) as applied to claims 1-3, 5-13, 18-23 and 53 above, and further in view of Shinohara et al. (U.S. Publication No. 2009/0200680) (“Shinohara”). [4] With respect to the limitations of claim 4, Ramachandra, Hirano and Tao teaches and/or renders obvious bitline driver chiplet is a first bitline driver chiplet and the wordline driver chiplet is a first wordline driver chiplet, as well as their orientation while being mounted to the front surface of the NAND wafer (See § XI.A.(1), rejection of claim 1 above). Ramachandra, Hirano and Tao is silent about the microelectronic package further comprising a plurality of bitline

§ 103Obviousnessclaims 14-15

Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandra et al. (U.S.

Examiner theory

Publication No. 2018/0102344) (“Ramachandra”) in view of Hirano et al. (U.S. Publication No. 2019/0341375) (“Hirano”) and Tao et al. (U.S. Publication No. 2018/0040587) (“Tao”) as applied to claims 1-3, 5-13, 18-23 and 53 above, and further in view of Itoh et al. (U.S. Publication No. 20080122064) (“Itoh”). [14] With respect to the limitations of claim 14, Ramachandra teaches a plurality of NAND wafers are arranged in a staircase configuration, such that each of the plurality of NAND wafers that is below the first NAND wafer is horizontally offset from the NAND wafer that is directly thereabove in the stack by a first offset distance in the first direction (Ramachandra; see Figure 2). Ramachandra, Hirano and Tao is silent about the NAND wafers also being offset by a second offset distance

§ 103Obviousnessclaims 16-17

Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandra et al. (U.S.

Examiner theory

Publication No. 2018/0102344) (“Ramachandra”) in view of Hirano et al. (U.S. Publication No. 2019/0341375) (“Hirano”) and Tao et al. (U.S. Publication No. 2018/0040587) (“Tao”) as applied to claims 1-3, 5-13, 18-23 and 53 above, and further in view of Kodama et al. (U.S. Publication No. 2008/0157393) (“Kodama”). [16] With respect to the limitations of claim 16, Ramachandra and Hirano teaches NAND wafers. However, Ramachandra, Hirano and Tao is silent about the plurality of NAND wafers being arranged in an alternating orthogonal configuration, such that long sides of each of the plurality of NAND wafers that is below the first NAND wafer are rotated 90 degrees relative to long sides of the NAND wafer that is directly thereabove in the stack. However, in the same field or endeavor, Kodama

§ 103Obviousnessclaims 51-52

Claims 51 and 52 are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandra et al. (U.S.

Examiner theory

Publication No. 2018/0102344) (“Ramachandra”) in view of Hirano et al. (U.S. Publication No. 2019/0341375) (“Hirano”) and Tao et al. (U.S. Publication No. 2018/0040587) (“Tao”) as applied to claims 1-3, 5-13, 18-23 and 53 above, and further in view of Leedy (U.S. Publication No. 20140043883). [51] With respect to the limitations of claim 51, Ramachandra teaches the bitline driver (Ramachandra; see #132 and/or #128 in Figure 4 and in ¶ [0030, [0032], [0039]) being configured to function as a bitline driver for the NAND wafer and the bitline driver being mounted to a front surface of the NAND wafer (id.; see Figure 4 showing #132 and/or #128 mounted on top of the NAND wafer). In addition, as set forth above, Tao teaches and/or renders obvious incorporating the utilization of direct bonding

Prior art consulted (7)

Identifier	Type	Name / Author	Link
US20180102344	patent publication	Ramachandra et al.	View ↗
US20190341375	patent publication	Hirano et al.	View ↗
US20180040587	patent publication	Tao et al.	View ↗
US20090200680	patent publication	Shinohara et al.	View ↗
US20080122064	patent publication

Procedural framework (15)

MPEP§ 1414·§ 1414.03(1)·§ 2111·§ 2111.01·§ 2111.01(I)·§ 2111.01(II)·§ 2111.01(IV)·§ 2181·§ 2144

Non-Final Office Action

Jan 24, 2025 · §103, §112, §251

Non-Final Office Action — all claims 1-50 rejected under §103 obviousness; claims 18, 21-22 also rejected under §112(b) indefiniteness

A response is due within three months from January 24, 2025, extendable to six months with fees. An attorney typically responds by amending claims to distinguish them from the cited references, arguing why the examiner's combinations are improper, or both. Requesting an examiner interview to discuss the rejections is common at this stage. An attorney typically handles this; if you'd like patentreply.ai to draft a response, click 'Get this drafted'.

Rejection groups (7)

pre-AIA § 103(a)Obviousnessclaims 1-2, 5-8, 10-13, 18-29, 34-37, 39-44, 49

Claims 1, 2, 5-8, 10-13, 18-29, 34-37, 39-44, and 49 are rejected under pre-AIA 35 U.S.C. 103(a) as obvious over US.

Examiner theory

Pub. No. 2018/0102344 A1 to Ramachandra et al. (“Ramachandra”) in view of US. Pub. No. 2019/0341375 A1 to Hirano et al. (“Hirano”). As to claim 1, Ramachandra teaches a microelectronic package, comprising: a substrate (#20 in Fig. 2 and in ¶ [0018]) having first and second opposite surfaces (bottom and top surfaces) each extending in first and second orthogonal directions (into the page and left to right); a NAND wafer (#24 in Fig. 2 and in ¶ [0020], “NAND” in [0029]) having a memory storage array (#126 in Fig. 2 and in ¶ [0029]) therein, the NAND wafer having element contacts (#66 in Fig. 3 and in ¶ [0025]) electrically connected with electrically conductive structure of the substrate (via #42 or #44 in Fig. 2 and 3 and in ¶ [0021-0022]), the NAND wafer being coupled to the first surface

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Rejection groups (5)

Prior art consulted (7)

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Rejection groups (7)

Prior art consulted (6)

Identifier	Type	Name / Author	Link
US20180102344A1	patent publication	—	View ↗
US20190341375A1	patent publication	—	View ↗
US8399974B1	us patent	—	View ↗
US20090200680A1	patent publication	—	View ↗
US20080122064A1	patent publication	—	View ↗
US20080157393A1	patent publication	—	View ↗